1. Technical Field
The present invention relates to an electrical structure, and associated method of fabrication, that reduces thermally induced strain in solder joints that couple a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card.
2. Related Art
A well-known method for coupling a chip to a chip carrier is that of controlled collapse chip connection (“C4”) in which a C4 solder ball couples a chip to a chip carrier. The C4 solder ball is coupled to a pad on the chip and the C4 solder ball is connected to the chip carrier by use of a solder joint at a solderable site on the chip carrier. The C4 solder ball has any composition that is well Known in the art, and typically comprises an alloy of lead and tin in such high lead/tin ratios as 90/10 or 97/3 by weight. Another C4 solder ball composition is a lead/indium alloy in a 50/50 ratio by weight.
When the above structure is heated or cooled, the solder joint is subject to strains that arise from the differential rate of thermal expansion of the chip and the chip carrier. For example, a chip typically comprises silicon and has a coefficient of thermal expansion (“CTE”) of about 3 to 6 ppm/° C. (ppm denotes parts per million). The chip carrier is typically a laminate comprising alumina or a laminate comprising an organic material. A alumina chip carrier has a CTE of about 6 ppm/° C., while an organic chip carrier has a CTE in the range of about 6 to 24 ppm/° C. The thermal stresses and consequent strains resulting from the CTE mismatch during thermal cycling may cause fatigue failure in the solder joint and consequent reduction in reliability as measured by the number of cycles that can be achieved prior to fatigue failure.
A method in the prior art for mitigating the effect of the CTE mismatch on fatigue life is filling the space between the chip and the chip carrier with a material that encapsulates the interconnecting structure, including the C4 solder ball, that joins the chip to the chip carrier, as described in U.S. Pat. No. 5,656,862 (Papathomas et al., Aug. 12, 1997, hereby incorporated by reference). The encapsulating material typically has a CTE of about 24 to 40 ppm/° C. and causes the whole structure to move as one composite structure during thermal cycling. The high stiffness of the encapsulating material enables the encapsulating material to accommodate the thermal stresses that would otherwise act at the solder joint. A material that may be used for this purpose is Hysol 45121 which has a stiffness of about 106 psi. A problem with using encapsulating material is that conditions, such as contamination or fracture of the encapsulating material, may prevent the encapsulating material from adequately adhering to the interconnecting structure. The resulting separation of the encapsulating material exposes the interconnecting structure, thereby negating the encapsulating material's role of reducing thermal stresses. Another difficulty is that the high encapsulant stiffness needed for effectively relieving thermal stresses unfortunately generates mechanical stresses on the interconnecting structure that may be high enough to weaken the structural integrity of the interconnecting structure. As the encapsulant stiffness diminishes, the mechanical stresses on the interconnecting structure decrease and the ability of the encapsulant to absorb shock and vibration increases. An additional consideration is that the encapsulating material interferes with reworkability of the chip-to-chip carrier structure for correcting a problem arising during the life cycle and testing phases of the structure.
Another method in the prior art for mitigating the effect of the CTE mismatch on fatigue life is a process disclosed in U.S. Pat. No. 5,641,113 (Somaki et al., Jun. 24, 1997, hereby incorporated by reference). Somaki discloses coupling a chip to a substrate by fusing together a first solder bump truncated sphere and a second solder bump truncated sphere. The fusing occurs after a first process and before a second process. The first process includes forming and connecting the first solder bump to the chip, coating the first solder bump with a non-conductive resin that is liquid at room temperature prior to being hardened, hardening the resin layer, and removing a portion of the resin layer so as to expose a surface of the first solder bump that will be fused with the second solder bump. After the first process, the fusing is accomplished by reflowing the first solder bump and second solder bump at a temperature that causes both the first solder bump and the second solder bump to melt and fuse together. Then the second process joins the second solder bump to the substrate. Unfortunately, this method is not practical for reworking the chip-to-substrate structure for correcting problems arising during the life cycle and testing phases of the structure. The reworkability is problematic, because the application of heat to decouple the fused first and second solder bumps will melt both the first and second solder bumps. As the chip and the substrate are pulled apart, molten solder will flow out of the resin layer leaving a partially or fully empty resin shell attached to the chip. This resultant chip configuration cannot be reworked at a practical cost and the chip has consequently become unusable.
There is a need for a method of reducing the thermal stresses that facilitates reworkability, eliminates the need for encapsulating material or enables an encapsulant of diminished stiffness to be used.